1. Field of the Invention
This invention relates to the field of microprocessors and, more particularly, to special registers within microprocessors.
2. Description of the Relevant Art
Superscalar microprocessors achieve high performance by executing multiple instructions per clock cycle and by choosing the shortest possible clock cycle consistent with the design. As used herein, the term "clock cycle" refers to an interval of time accorded to various stages of an instruction processing pipeline within the microprocessor. Storage devices (e.g. registers and arrays) capture their values according to the clock cycle. For example, a storage device may capture a value according to a rising or falling edge of a clock signal defining the clock cycle. The storage device then stores the value until the subsequent rising or falling edge of the clock signal, respectively. The term "instruction processing pipeline" is used herein to refer to the logic circuits employed to process instructions in a pipelined fashion. Although the pipeline may be divided into any number of stages at which portions of instruction processing are performed, instruction processing generally comprises fetching the instruction, decoding the instruction, executing the instruction, and storing the execution results in the destination identified by the instruction.
Microprocessor designers often design their products in accordance with the x86 microprocessor architecture in order to take advantage of its widespread acceptance in the computer industry. Because the x86 microprocessor architecture is pervasive, many computer programs are written in accordance with the architecture. X86 compatible microprocessors may execute these computer programs, thereby becoming more attractive to computer system designers who desire x86-compatible computer systems. Such computer systems are often well received within the industry due to the wide range of available computer programs.
The x86 microprocessor architecture includes general and special registers. General registers are registers that are readily accessible to all instructions. For example, in the x86 architecture eight general registers (EAX, EBX, ECX, EDX EBP, ESI, EDI and ESP) are defined. The x86 microprocessor architecture also includes special registers. For example, the x86 architecture defines six segment registers (CS, SS, DS, ES, FS and GS), a flag register (EFLAGS) and an instruction pointer register (EIP). In addition, the special registers include a set of model specific registers (MSRs) that may differ between various implementations of an x86 microprocessor. For example, a Time Stamp Counter is not defined as part of the x86 architecture. Some implementations of an x86 microprocessor, however, include a Time Stamp Counter as a special register. The Time Stamp Counter may be used to monitor the performance of a microprocessor. Other examples of special register include temporary registers, microcode registers and processor feature control registers. These registers may be distributed throughout the microprocessor.
Resources within a microprocessor include special registers and other resources such as caches. Access to microprocessor resources is typically accomplished by special instructions. For example, a special instruction to flush the instruction cache may be defined. Likewise, a special instruction for reading or writing to microcode registers may be defined. Typically, when new resources are added to a microprocessor, new special instructions are defined to access those resources. Defining new instructions requires the modification of a significant portion of the microprocessor. For example, adding an instruction to flush the instruction cache may require the modification of the decode unit to recognize the opcode of the new instruction, the modification of the microcode unit to implement the function of the new instruction, the addition of signal lines from the microcode unit to the instruction cache to signal the function of the new instruction, and the modification of the instruction cache to receive the signal and execute the function of the new instruction.
The modification of the microprocessor to accommodate new resources creates significant design and testing problems. Modifying the circuitry of the microprocessor may introduce debug problems, timing problems and speed paths. What is desired is a flexible way to access resources that does not require significant redesign to add new resources.